1. Field of the Invention
The invention relates in general to integrated electronic circuits, and more particularly, to timing analysis in electronic circuit design and testing.
2. Description of the Related Art
Recent advances in process technology scales the aspect ratio of wires to be taller and thinner to control wire resistance. A side effect of this scaling is that coupling capacitance between wires becomes the dominant portion of the total wire capacitance. See, K. L. Shepard, “Design methodologies for noise in digital integrated circuits”, Proceedings of the Design Automation Conference, pages 94-99, June 1998; and F. Dartu, L. Pileggi, “Calculating worst-case gate delays due to dominant capacitance coupling”, Proceedings of the Design Automation Conference, pages 46-51, June 1997. At the same time, the signal transition times have become faster resulting in stronger aggressors on adjacent victim wires. See, F. Dartu et al. Another side effect of process advancement is the faster scaling of cell internal delay than the interconnect delay, making accurate analysis of interconnect delay important.
The importance of the crosstalk effects on delay has grown significantly with recent technology advances. For example, crosstalk delay has become a more prominent element of timing analysis during integrated circuit design due to factors such as, (i) increase in coupling-to-total capacitance ratio, (ii) decrease in supply voltage resulting in a reduction of gate overdrive (iii) shortening of clock period causing transition waveforms to play a bigger role, and (iv) tighter timing margins requiring more accurate timing analysis and less overestimation of delay.
Delay calculation in the presence of crosstalk typically involves finding a worst-case delay among possible aggressor alignments and aggressor waveforms. Determination of delay in the presence of aggressor-induced noise is a challenging task due to factors such as, (i) delay being sensitive to aggressor/victim alignment, (ii) linear models for switching drivers potentially being inaccurate due to drastic variation of impedance during transition, (iii) effective capacitance principle requiring modification (See, F. Dartu et al), and (iv) waveforms potentially becoming irregular in the presence of noise, making the conventional metric of delay measurement non-robust.
In view of the sensitivity of crosstalk delay to factors such as, aggressor alignment, the nonlinearity of drivers, and aggressor timing window constraints, a search for the worst-case (WC) alignment may be approached using constrained nonlinear optimization techniques. However, optimization in a multidimensional space of aggressor alignments with each iteration requiring simulation of a nonlinear circuit can be prohibitively expensive. The crosstalk delay analysis task is further complicated by the potential for a unique waveform response of each receiver of a victim net to a given input transition, such that a WC aggressor alignment for one receiver may not be the same for another.
Another challenge with analyzing a crosstalk induced delay change arises from the potential for crosstalk to distort a victim switching waveform. A distorted waveform may deviate from the input waveforms used in delay characterization of a receiving gate, resulting in inaccuracy in slew dependent delays in a downstream logic cone. If the crosstalk impact is severe, the victim waveform may even become non-monotonic (bumpy), the effect of which may not be properly modeled in existing gate delay systems.
There have been prior proposals for analysis of crosstalk induced delay. R. Arunachalam, K. Rajagopal, and L. Pileggi, Taco, “Timing analysis with coupling”. Proceedings of the Design Automation Conference, pages 266-269, June 2000 teach that static timing analysis (STA) can be used to calculate delay while accounting for effects of switching aggressors using a heuristic-based Miller factor, which is applied to coupling capacitance before it is grounded. This approach is believed to be too conservative and inaccurate to be successfully used for modern design constraints. Another approach is based on computation of a noisy transition—transition in the presence of switching aggressors, and using it for determining new slews and delays. In several studies the linear superposition principle was applied to the nominal transition with a noisy waveform on the victim net computed separately. See, F. Dartu, et al.; R. Arunachalam, et al.; and P. D. Gross, R. Arunachalam, K. Rajagopal, and L. Pileggi, “Determination of worst-case aggressor alignment for delay calculation”, Proceedings of the ICCAD, pages 212-219, November 1998. The nominal transition is computed using a linear Thevenin model for the victim driver with all aggressors kept quiet. The alignment between nominal transition on the victim and transitions on the aggressors was chosen based on noise pulse width and height. However, since the noise wave was computed for a quiet victim driver and not a switching one, the alignment used in the mentioned studies could be inaccurate.
S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and J. Zuo, “Driver modeling and alignment for worst-case delay noise”, Proceedings of the Design Automation Conference, pages 720-725, June 2001, proposed that alignment between the victim and aggressors should be determined using characteristics of a receiving gate. The proposed approach is based on a pre-characterized 4-D look-up table representing alignment as a function of nominal slew rate, noise peak and width on the victim net and output load of receiving gate.
Current-based models for gates have been proposed. See, J. F. Croix, and D. F. Wong, “Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models”, In Proceedings of the Design Automation Conference, 386-391, June 2003; and V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon and R. Levy, “Noise propagation and failure criterion for VLSI designs” Proceedings of the ICCAD, pages 587-594, November 2002. However, there is no teaching of how such current model is to be integrated in a flow of crosstalk delay change analysis.
FIGS. 14A and 14B illustrate one aspect of a prior methodology for measurement of aggressor-induced crosstalk delay. FIG. 14A is an illustrative drawing of a set of curves that represent victim signal transitions from VDD to ground. Each curve represents a different alignment of a victim signal transition with an aggressor signal. In each case, the aggressor signal induces a bump in the victim signal transition. The curves are non-monotonic due to the aggressor-induced bumps. Victim net signal transition delay is measured in terms of the time at which the victim signal crosses the Vref level. The curves of FIG. 14A illustrate that an aggressor-induced bump can cause the victim signal to cross Vref multiple times. A second crossing increases the measured victim signal transition delay according to the conventional methodology, since the delay should be measured based on the latest crossing of Vref.
FIG. 14B is an illustrative drawing of a curve representing victim signal transition delay versus aggressor alignment. The heavy dots on the delay curve denote correspondent crossing times of Vref on the noisy transitions shown in FIG. 14A. The curve of FIG. 14B shows that victim signal transition delay depends upon aggressor alignment. Unfortunately, the non-monotonic waveforms of FIG. 14A result in a ‘cliff’ in the curve of FIG. 14B methodology. The last curve in FIG. 14A does not have a bump crossing Vref, which engenders the cliff in delay curve in FIG. 14B. This prior methodology is not robust because even a relatively small change in a circuit parameter (e.g., driver size, supply voltage, etc) and/or aggressor alignment on a particular victim net can result in a disproportionate change in measured victim signal delay due to the such cliff.
Thus, there has been a need for more robust and accurate measurement of aggressor induced crosstalk delay. The present invention meets this need.